Chiplet technology expands possibilities for compact and scalable semiconductor designs

By Staff Report March 11, 2025 11:36 am IST

Chiplet technology offers smaller and more compact designs with simplified structures, enabling the integration of GPU, CPU, and IO components into a more simplified, unified design.

Smaller and more compact designs with simplified structures can be achieved with chiplet technology. IDTechEx’s report, Chiplet Technology 2025-2035: Technology, Opportunities, Applications. Unpacks the benefits and challenges of developing chiplet technology compared with competing semiconductor designs and their best-suited applications.

Chiplet characteristics

Chiplets allow for GPU, CPU, and IO components to become miniaturised to suit the rise of smaller and more compact devices and hardware and can bring about a means of integrating various functions into a more simplified, unified design. Easy scalability, faster innovation, and cost-effectiveness are all benefits of chiplets, alongside enhanced functionality and performance efficiency.

Chiplets can be developed faster than monolithic SoCs and multi-chip SiPs and largely be reused. They are expected to enable new functionalities that are not likely to be achieved with monolithic designs alone, particularly in fields such as AI, IoT, and advancing computing systems.

However, although chiplets can be largely adopted in smartphones, automotive systems, high-performance computing (HPC), data centres, and cloud computing, they are not intended to replace monolithic SoCs, which have higher performance efficiencies.

Semiconductor manufacturing processes

Semiconductor nodes progressively getting smaller in the future may help improve chiplet and monolithic designs by increasing component density and function density. Monolithic integration is currently largely used for HPC due to its performance qualities and power efficiency, while chiplets can use less advanced nodes for specialised components with reduced costs and shorter time to market.

Another future trend predicted by IDTechEx is advanced 3D stacking, whereby interconnectivity and thermal management can be improved for chiplet and monolithic designs, moving away from 2D structures to 3D, and enabling more compact, high-performance systems.

Chiplet technology trends

Achieving universal interconnect standards can enable interoperability for chiplets from different manufacturers and increase their use versatility. This will be particularly useful as interest in chiplets grows worldwide in countries such as the US, China, Germany, and Japan. The Chiplet Design Exchange (CDX) is striving to achieve open formats for chiplet designs in order to overcome challenges with standardisation, which will be necessary to facilitate the wider adoption of chiplets across various sectors.

Communication between chiplets will also be vital to achieve interconnection and reliability. IDTechEx reports numerous technologies currently being developed to achieve these, including Universal Chiplet Interconnect Express (UCIe) and Bunch of Wires (BoW).

New testing approaches are emerging to address the challenges associated with chiplet technologies. IDTechEx highlights the use of design-for-test (DFT) and built-in-self-test (BIST) strategies as economically viable solutions for testing chiplets. These methods help overcome the complexity of testing interconnected chiplets by enabling fault detection, diagnosis, and optimisation directly within the chiplet design, reducing reliance on external test equipment. Additionally, advanced techniques like hierarchical testing and inter-chiplet communication testing are being developed to ensure comprehensive test coverage across chiplet interfaces.

While testing strategies focus on ensuring functionality and reliability, advancements in bonding methods, such as copper hybrid bonding, are revolutionising chiplet integration. Copper hybrid bonding eliminates traditional solder bumps, enabling ultra-fine pitch connections with improved electrical and thermal performance. This bonding technique supports higher interconnect density and reduces parasitic resistance, making it a critical enabler for compact and high-performance chiplet systems.

For more information on chiplet technology and the wider semiconductor market, visit IDTechEx’s report, Chiplet Technology 2025-2035: Technology, Opportunities, Applications. And the wider portfolio of Semiconductors, Computing & AI Research Reports, and Subscriptions. Downloadable sample pages are available for all IDTechEx reports.